The present invention relates to a disk control device or a storage device which stores a large amount of information. More particularly the present invention relates to apparatus for use in a disk control device or a storage device that prevents system downtime and a degeneration in the operation of the device due to a failed part in the device or when the device has partially failed. Even more particularly the present invention provides apparatus that allows for high availability or maintainability in a disk control device or a storage device in which failed parts are exchanged without stopping the device.
In large data storage equipment or large storage systems which store customer information, such as an on-line banking system, it is highly desired to have equipment or a system wherein the stored data is continually available and the equipment or system is easily maintainable. In such equipment or system the operation thereof does not degenerate when a failure has occurred in any part of the equipment or failure. Further, in such equipment or system failed parts can be exchanged without stopping operation thereof.
Storage devices using magnetic disk storage units as a storage media have been proposed. Such systems are known as Redundant Arrays of Inexpensive Disks (RAID) systems. Magnetic disk storage units are quite suitable in such an application since they provide large storage capacity for a unit price. Recently a non-stop system has been proposed by adopting a RAID system in which availability and maintainability is provided by exchanging the magnetic disk units.
FIG. 1 is an example of the construction of a conventional large storage system. A disk controller (DKC) 101 is connected to a host processor 102 as an upper unit through channels 110 and 111. The DKC 101 is also connected to a disk unit (DKU) 103 as an lower unit through drive buses 112, 113, 114 and 115. Various modules described below are connected to common buses bus0 and bus1117 and 118 respectively wired on a platter (PL) which is the wiring base inside the DKC 101.
Memory modules 119 and 120 are semiconductor memory (CACHE) containing a copy of data stored in DKU 103, and data which are transferred from the host processor 102 and stored in DKU 103. The channel adapter modules (CHA) 121 and 122 are connected to the channels 110 and 111. The CHA 121 and 122 control data transfer between the host processor 102 and the memory modules 119 and 120. Disk adapter modules (DKA) 123 and 124 are connected to drives 125 to 128 in DKU 103 through the drive paths 112 to 115. The DKA""s 123 and 124 control data transfer between the memory modules 119 and 120 and the drives 125 to 128. The memory modules 119 and 120 also store control information required for data transfer control which CHA 121, 122 and DKA 123, 124 control. The common buses 117 and 118 are used as paths for data transfer and access for control information between CHA 121, 122 or DKA 123, 124 and memory modules 119 and 120, and for communication between CHA 121, 122 and DKA 123, 124.
The common buses 117 and 118 are composed of a plural number of buses which are physically independent from each other, and their transfer modes are selected by a bus command during the transfer. There are a sequential data transfer mode in which buses logically operate as one bus, and a transaction data transfer mode in which each of the buses operates independently. In the DKC 101 all of hardware parts excepting PL 116 are multiplexed, thereby preventing a complete stop in DKC 101 due to a degenerative process resulting from a partial failure. Non-stop exchanging in all of hardware parts excepting PL1116 is possible by non-disruptive exchange of each module. However, there are some problems described below when a part of the device has failed.
FIG. 8 illustrates a configuration, similar to that described in Japanese unexamined patent publication 04-276698, of a conventional wiring board, wherein two wiring boards are provided and one of the wiring boards has one of the bus lines and the other of the wiring boards has the other of the bus lines. In FIG. 8, the two wiring boards are shown as being attached back to back and each printed wiring substrate (MP) is shown as being connected to both of the bus lines of the two wiring boards. Although two wiring boards are disclosed as being connected to each other using a printed circuit board, the details of the printed circuit board are not shown.
In a computer system constructed according to that illustrated in JP-4-276698 system downtime due to bus degeneration can be avoided. Such is possible even when the failure is due to the breaking of wires in the PL itself. However, the disadvantage is that the system must be stopped when the failed bus is to be exchanged, because the failed bus is included in the PL. A further, disadvantage is that the performance of the computer system deteriorates due to the limited transfer bus mode in the operation performed by the degenerated bus.
An object of the present invention is to provide an apparatus which connects the common buses of different platters (PL""s) to each other by use of a connector, wherein each PL is divided into two, thereby allowing a failed PL to be exchanged during operation of the other PL.
Another object of the present invention is to provide an apparatus which permits access to common resources across clusters by use of a communication method, wherein a data transfer mode can be selected based on the state of the clusters.
Yet another object of the present invention is to provide apparatus which improves bus performance and allows for non-stop maintenance for common bus failures in a computer system represented by a large storage device.
The present invention provides a disk control device or a storage device having a plurality of clusters interconnected to each other by a common resource. Each cluster includes a plurality of common buses which are connected to a disk controller (DKA), a channel controller (CHA) and a cache (CACHE). The common resource connects each of the common buses to each other between the clusters.
The common resource includes shared memory and cache memory which allows access from other clusters. The common resource provides lock bits in a control table in the shared memory for indicating whether access to resources corresponding to the bits is possible. Also provided is a microprocessor (MP) communication function using interruption signals between microprocessors in each CHA and DKA to effect communication from a module in one cluster to that in another cluster. This function allows for synchronization to be established in bus modes between clusters and to resolve conflicts in accesses to the common resource. Bus transfer performance in the system increases relative a system in which parallel transfer using common buses across plural clusters is conducted.
The structure of the present invention allows for multiple clusters to be connected to each other and can be applied not only to a large storage device adopting RAID technology but also to a device adopting SLED technology.